1. Field of the Invention
This invention relates generally to data processing systems and, more particularly, to high performance data processing systems that can be implemented using readily available components.
2. Description of the Related Art
As the desire for improved performance in data processing systems has increased, the design of the data processing systems has become more complex. For example, the use of a data processing system implemented using pipelined techniques has become common. In the pipeline technique, the processing function of a data processing system is divided into a multiplicity of subfunctions. The subfunctions are chosen so that each subfunction occupies a determined timing period (or cycle). The execution of an instruction involves the sequential execution of each subfunction. The execution of each subfunction is independent of the execution of the preceding or succeeding subfunction, permitting an instruction to begin and, consequently, to end during every timing cycle. The number of subfunctions into which the execution of an instruction can be divided is also the number of instructions that can be in simultaneous execution in a pipelined data processing system. Although the total time required for execution of each instruction is generally (significantly) longer than the execution of the instruction without pipeline techniques, instruction sequences can be executed more rapidly. The more rapid execution of an instruction sequence (once the pipelined data processing system has all subfunction units executing instructions) is achieved at the cost of greater complexity of the data processing system.
In addition, as data processing systems have increased in complexity, the requirement for specialized components has increased. Similarly, an attempt to improve the performance of a data processing system can frequently lead to more and more complex components. In either case of specialized components or more complex interconnection of the components, the result is increased cost of the data processing system.
The present invention is a result of a strategy to build a high performance central processing unit by attempting to keep the unit as simple as possible and by attempting to design the unit so that commercially available components, as opposed to specially designed components, can be used to implement the central processing unit. As an example, the format and the length of an instruction word must be selected and has implications throughout the architecture of the central processing unit. The size of an instruction word and the size of a data word are important in the design of a central processing unit. In particular, the instruction word frequently has been implemented by a variable length instruction word format or by parameters. Furthermore, to the extent that the instruction word has fields that have identical interpretations, the decoding apparatus for the instruction word can be simplified.
A need has therefore been felt for a high performance central processing unit that avoids many of the complexities of other high performance central processing unit and can be fabricated relatively easily.